1. Field of the Invention
The present invention generally relates to semiconductor memories and, more particularly, to a test structure for determining leakage in dynamic random access memory cells.
2. Background Description
Dynamic Random Access Memory (DRAM) cells are well known. A DRAM cell is essentially a capacitor for storing charge coupled to a pass transistor (also called a pass gate or access transistor) for transferring charge to and from the capacitor. The absence or presence of charge on the capacitor corresponds to a logic value of data stored in the cell. Because cell size determines chip density, size and cost, reducing cell area is one of the DRAM designer""s primary goals.
Reducing cell area is done, normally, by shrinking feature sizes to shrink the cell. In addition to shrinking the cell features, the most effective way to reduce cell area is to reduce the largest feature in the cell, typically, the area of the storage capacitor. Unfortunately, shrinking the capacitor area reduces capacitance and, consequently, reduces stored charge. Reduced charge means what is stored in the DRAM is more susceptible to noise, soft errors, leakage and other typical DRAM problems. Consequently, a DRAM cell designer""s goal is also to maintain storage capacitance, thereby maximizing stored charge without sacrificing cell area.
One way to reduce DRAM cell size without necessarily reducing storage capacitance is to use trench capacitors in the cells. Typically, trench capacitors are formed by etching long deep trenches in a silicon wafer, selectively doping the trench sidewalls, coating the trench with a dielectric layer and then, filling the coated trench with polysilicon or amorphous silicon to form a cell capacitor on its side in the trench. Thus, the surface area required for the storage capacitor is dramatically reduced without sacrificing capacitance, and more importantly, stored charge.
However, even though the storable charge may be maintained, cell leakage may still be a problem. Typical cell leakage occurs at pn junctions. Thus, the capacitor plate, which is surrounded by dielectric, is the optimum charge storage node for minimized leakage. However, to transfer data in and out of the cell, the capacitor plate must be connected to a cell access transistor, typically a field effect transistor (FET). This connection is to the FET""s source diffusion, i.e., a pn junction, which becomes the primary source of cell leakage. To understand how cell leakage occurs, this connection must be characterized precisely.
For state of the art DRAM cells, the trench capacitor plate is strapped to the source diffusion with doped polysilicon. Typically, the doped polysilicon strap forms a pn junction which is, or merges with the source diffusion junction. State of the art leakage measurement techniques measure the combined strap and source diffusion leakage. Leakage at the strap junction is difficult to accurately quantify from the total DRAM cell leakage measured using these state of the art test techniques. So, typically, the strap junction leakage must be estimated from the total cell leakage. Without precise measurements, it is difficult to determine how to further improve cell structures to reduce cell leakage.
Thus there is a need for DRAM cell capacitor connection test structures and methods for characterizing and testing such structures.
It is therefore a purpose of the present invention to decrease the Dynamic Random Access Memory (DRAM) cell leakage;
It is another purpose of the present invention to accurately measure DRAM cell storage capacitance leakage;
It is yet another purpose of the present invention to characterize DRAM cell trench capacitor plate leakage;
It is yet another purpose of the present invention to characterize DRAM cell trench capacitor plate to access transistor connection leakage;
It is yet another purpose of the present invention to characterize DRAM cell trench capacitor leakage in order to provide DRAM cell designers with cell characterization information for improving DRAM cell designs.
The present invention is a test structure and method for determining DRAM cell leakage. The test structure includes a pair of buried strap test structures. Each buried strap test structure includes multiple trench capacitors formed in a silicon body. Each trench capacitor is connected to a trench sidewall diffusion by at least one buried strap. An n-well ring surrounds each buried strap test structure and divides the buried strap test structure into two separate array p-wells, one being a contact area and the other a leakage test area. For each buried strap test structure, the contact area includes contacts to the trench capacitor plates for that buried strap test structure. In one buried strap test structure, a layer of polysilicon, essentially covers the trench capacitors in the leakage test area to block source/drain region formation there. The other of the two buried strap test structures includes polysilicon lines that simulate wordlines with source and drain regions formed on either side. A buried n-band contacts both n-well rings, essentially forming an isolation tub around each array well. Cell leakage is measured by measuring leakage current in each buried strap test structure, individually. Then, individual leakage components are extracted from the measured result.